View MB84SD23280FE-70_1274584.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions.
TM
memory
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50222-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
64M (x16) FLASH MEMORY & 8M (x16) SRAM
MB84SD23280FA/MB84SD23280FE-70
s FEATURES
* Power supply voltage of 1.65 V to 1.95 V * High performance 70 ns maximum access time (Flash) 70 ns maximum access time (SRAM) * Operating Temperature -30 C to +85 C * Package 73-ball FBGA
(Continued)
s PRODUCT LINEUP
Flash Memory Supply Voltage (V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) VCCf* = 1.8 V 70 70 20
+0.15V -0.15 V
SRAM VCCs* = 1.8 V 70 70 35
+0.15V -0.15 V
*: Both VCCf and VCCs must be in recommended operation range when either part is being accessed.
s PACKAGE
73-ball plastic FBGA
(BGA-73P-M03)
MB84SD23280FA/MB84SD23280FE-70
(Continued)
* FLASH MEMORY * 0.17 m process technology * Simultaneous Read/Write operation (Dual Bank) * FlexBankTM *1 Bank A: 16M bit (16KB x 4 and 64KB x 31) Bank B: 16M bit (64KB x 32) Bank C: 16M bit (64KB x 32) Bank D: 16M bit (16KB x 4 and 64KB x 31) * Minimum 100,000 program/erase cycles * Sector Erase Architecture Four 8K words, a hundred twenty-eight 32K words sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase. * WP Input Pin At VIL, allows protection of all sectors, regardless of sector protection/unprotection status At VIH, allows removal of sector protection * Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector * Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Automatic sleep mode When address remain stable, the device automatically switches itself to low power mode * Low VCC write inhibit * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device resumes the erase operation * Sector Protection Software command sector locking * Please Refer to "MBM29BS64LF" Datasheet in Detailed Function *SRAM * Power Dissipation Operating : 50 mA Max Standby :15 A Max * Power Down Features using CE1s and CE2s * Data Retention Supply Voltage: 1.0 V to 1.95 V * CE1s and CE2s Chip Select * Byte Data Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8)
*1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MB84SD23280FA/MB84SD23280FE-70
s PIN ASSIGNMENT
FBGA (TOP VIEW) Marking Side
A10 N.C.
B10 N.C. D9 A15 C8 A11 C7 A8 B6 N.C. B5 N.C. C6 WE C5 WP C4 LB C3 A7 D8 A12 D7 A19 D6 CE2s D5 RESET D4 UB D3 A6 D2 A3 E9 A21 E8 A13 E7 A9 E6 A20 E5 RDY E4 A18 E3 A5 E2 A2
F10 N.C. F9 N.C. F8 A14 F7 A10
G10 N.C. G9 A16 G8 N.C. G7 DQ6 H9 N.C. H8 DQ15 H7 DQ13 H6 DQ4 H5 DQ3 J9 VSS J8 DQ7 J7 DQ12 J6 VCCs J5 VCCf J4 DQ10 J3 DQ0 J2 CE1s K8 DQ14 K7 DQ5 K6 N.C. K5 DQ11 K4 DQ2 K3 DQ8
L10 N.C.
M10 N.C.
L6 N.C. L5 N.C.
F4 A17 F3 A4 F2 A1 F1 N.C.
G4 DQ1 G3 VSS G2 A0 G1 N.C.
H4 DQ9 H3 OE H2 CEf
A1 N.C.
B1 N.C.
C1 N.C.
L1 N.C.
M1 N.C.
(BGA-73P-M03)
3
MB84SD23280FA/MB84SD23280FE-70
s PIN DESCRIPTION
Pin Configuration Pin Name A18 to A0 A21, A20, A19 DQ15 to DQ0 CEf CE1s CE2s OE WE RDY UB LB RESET WP N.C. VSS VCCf VCCs Address Inputs (Common) Address Inputs (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready Outputs (Flash) Open Drain Output Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin (Flash) Write Protect (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM) Function Input/Output I I I/O I I I I I O I I I I Power Power Power
s BLOCK DIAGRAM
VCCf A21 to A0 A21 to A0
WP
VSS RDY
RESET CEf
64 M bit Flash Memory DQ15 to DQ0
DQ15 to DQ0 VCCs A18 to A0 DQ15 to DQ0 VSS
LB UB WE OE CE1s CE2s
8 M bit SRAM
4
MB84SD23280FA/MB84SD23280FE-70
s DEVICE BUS OPERATIONS
User Bus Operations Operation*1, *3 Full Standby CEf CE1s CE2s OE H H Output Disable L Read from Flash*2 Write to Flash L L H X L H X H X H X L X L H X L X L X L H X H X H L H WE X H X H H L LB X X H X X X L Read from SRAM H L H H L L Write to SRAM Flash All Sector Write Protection*4 Flash Hardware Reset H L H X L H L X X X H X X X L X X X X X X UB X X H X X X L L H L L H X X DQ7 to DQ0 High-Z High-Z High-Z High-Z DOUT DIN DOUT High-Z DOUT DIN High-Z DIN X High-Z DQ15 to DQ8 High-Z High-Z High-Z High-Z DOUT DIN DOUT DOUT High-Z DIN DIN High-Z X High-Z H L L X H X H X H H X H H X RESET H WP*4 X
Legend : L = VIL, H = VIH, X = VIL or VIH. See "sDC CHARACTERISTICS" for voltage levels. *1: Other operations except for this indicated table are prohibited. *2: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: At WP=VIL, all sectors are protected.
5
MB84SD23280FA/MB84SD23280FE-70
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins * VCCf Supply * VCCs Supply * Symbol Tstg TA VIN VOUT VCCf VCCs Rating Min -40 -30 -0.3 -0.3 -0.2 -0.5 Max +125 +85 VCCf + 0.1 VCCs + 0.1 +2.5 +2.5 Unit C C V V V V
* : Minimum DC voltage on input or l/O pins are -0.5 V. During voltage transitions, inputs may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input and l/O pins are VCC +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature VCCf Supply Voltages VCCs Supply Voltages Symbol TA VCCf VCCs Value Min -30 +1.65 +1.65 Max +85 +1.95 +1.95 Unit C V V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
6
MB84SD23280FA/MB84SD23280FE-70
s DC CHARACTERISTICS*1, *2
Parameter Input Leakage Current Output Leakage Current Flash VCC Active Read Current *3 Flash VCC Active Write Current *4 Flash VCC Active Current (Read-While-Program)*5 Flash VCC Active Current (Read-While-Erase)*5 SRAM VCC Active Current SRAM VCC Active Current Symbol ILI ILO ICC1f ICC2f ICC3f ICC4f ICC1s ICC2s Test Conditions VIN = VSS to VCCf, VCCs VOUT = VSS to VCCf, VCCs CEf = VIL, OE = VIH, WEf = VIH CEf = VIL, OE = VIH, VPP = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH VCCs = VCCs Max, tCYCLE =10 MHz CE1s = VIL, CE2s = VIH CE1s = 0.2 V, CE2s = VCCs - 0.2 V tCYCLE = 10 MHz tCYCLE = 1 MHz 5 MHz 1 MHz Value Min -1.0 -1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- Flash SRAM Flash SRAM Flash SRAM -0.2 VCCf-0.2 1.6 -- -- VCCf-0.1 Typ -- -- 12 3.3 15 25 25 -- -- -- 0.2 0.2 -- -- -- -- -- -- -- -- -- -- Max +1.0 +1.0 16 5 40 60 60 50 50 10 10 10 14 14 0.2 VCCf+0.2 VCCs+0.2 0.1 0.4 -- -- 1.4 Unit A A mA mA mA mA mA mA mA A A A A V V V V V V V
Flash VCC Standby Current Flash VCC Standby Current (Standby, RESET) *6 SRAM VCC Standby Current SRAM VCC Standby Current Input Low Level Input High Level Flash Output Low Level SRAM Output Low Level Flash Output High Level SRAM Output High Level Flash Low VCC Lock-Out Voltage
ISB1f ISB2f ISB1s ISB2s VIL VIH VOL VOH VLKO
VCCf = VCCf Max, CEf = RESET = Vcc 0.2 V, VIN < 0.2 V VCCf = VCCf Max, RESET = VIL CE1s > VCCs - 0.2 V, CE2s > VCCs - 0.2 V CE2s < 0.2 V
VCCf = VCCf Min, IOL = 1.0 mA VCCs = VCCs Min, IOL = 2.1 mA VCCf = VCCf Min, IOH = -0.1 mA
VCCs = VCCs Min, IOH = -0.5 mA VCCs-0.5 -- 1.0
*1 : All voltage are referenced to VSS. *2 : IOUT depends on the output load conditions. *3 : The ICC current listed includes both the DC operating current and the frequency dependent component. *4 : ICC active while Embedded Algorithm (program or erase) is in progress. *5 : Embedded Algorithm (program or erase) is in progress. (@5 MHz) *6 : Automatic sleep mode enables the low power mode when address remain stable for tACC + 60 ns.
7
MB84SD23280FA/MB84SD23280FE-70
s AC CHARACTERISTICS
* CE Timing Parameter CE Recover Time CE Hold Time Symbol JEDEC -- -- Standard tCCR tCHOLD Condition -- -- Value Min 0 3 Unit -- --
* Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CE1s
WE
tCHOLD tCHOLD
tCCR
tCCR
CE2s
8
MB84SD23280FA/MB84SD23280FE-70
s SECTOR LOCK/UNLOCK COMMAND
The sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. When the device is first powered up, all sectors are locked. To unlock a sector, the system must write the sector lock/unlock command sequence. Two cycles are first written: addresses are don't care and data is 60h. During the third cycle, the sector address (SLA) and unlock command (60h) is written, while specifying with address A6 whether that sector should be locked (A6 = VIL) or unlocked (A6 = VIH). After the third cycle, the system can continue to lock or unlock additional cycles, or exit the sequence by writing F0h (reset command). * Flash Characteristics Please refer to "s 64M FLASH MEMORY for MCP 1.8 V". * SRAM Characteristics Please refer to "s 8M SRAM for MCP 1.8 V".
9
MB84SD23280FA/MB84SD23280FE-70
s 64M FLASH MEMORY for MCP 1.8 V
1. Flexible Sector-erase Architecture on FLASH MEMORY
* Sixteen 4K words, and one hundred twenty-six 32K words. * Individual-sector, multiple-sector, or bulk-erase capability.
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 : 16KB : 16KB : 16KB : 16KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB 000000h 002000h 004000h 006000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 1FFFFFh SA67 : 64KB SA68 : 64KB SA69 : 64KB SA70 : 64KB SA71 : 64KB SA72 : 64KB SA73 : 64KB SA74 : 64KB SA75 : 64KB SA76 : 64KB SA77 : 64KB SA78 : 64KB SA79 : 64KB SA80 : 64KB SA81 : 64KB SA82 : 64KB SA83 : 64KB SA84 : 64KB SA85 : 64KB SA86 : 64KB SA87 : 64KB SA88 : 64KB SA89 : 64KB SA90 : 64KB SA91 : 64KB SA92 : 64KB SA93 : 64KB SA94 : 64KB SA95 : 64KB SA96 : 64KB SA97 : 64KB SA98 : 64KB SA99 : 64KB SA100: 64KB SA101: 64KB SA102: 64KB SA103: 64KB SA104: 64KB SA105: 64KB SA106: 64KB SA107: 64KB SA108: 64KB SA109: 64KB SA110: 64KB SA111: 64KB SA112: 64KB SA113: 64KB SA114: 64KB SA115: 64KB SA116: 64KB SA117: 64KB SA118: 64KB SA119: 64KB SA120: 64KB SA121: 64KB SA122: 64KB SA123: 64KB SA124: 64KB SA125: 64KB SA126: 64KB SA127: 64KB SA128: 64KB SA129: 64KB SA130: 16KB SA131: 16KB SA132: 16KB SA133: 16KB 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3FA000h 3FC000h 3FE000h 3FFFFFh
BANK D
BANK C
Sector Architecture 10
BANK A
BANK B
MB84SD23280FA/MB84SD23280FE-70
* FlexBankTM Architecture Bank A B C D Quantity 4 31 32 32 31 4 Size 8K words 32K words 32K words 32K words 32K words 8K words
* Simultaneous Operation Case 1 2 3 4 5 6 7
Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode *
Bank 2 Status Read mode Autoselect mode Program mode Erase mode * Read mode Read mode Read mode
* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) meant to specify each of the Banks.
11
MB84SD23280FA/MB84SD23280FE-70
* Sector Address Table Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 Bank D SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Sector Size 8 Kwords 8 Kwords 8 Kwords 8 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 000000h to 001FFFh 002000h to 003FFFh 004000h to 005FFFh 006000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh
(Continued)
12
MB84SD23280FA/MB84SD23280FE-70
Bank
Sector SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords
(x16) Address Range 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh
Bank C
(Continued)
13
MB84SD23280FA/MB84SD23280FE-70
Bank
Sector SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords
(x16) Address Range 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh 2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh
Bank B
(Continued)
14
MB84SD23280FA/MB84SD23280FE-70
(Continued) Bank Sector SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 Bank A SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 8 Kwords 8 Kwords 8 Kwords 8 Kwords (x16) Address Range 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh 370000h to 377FFFh 378000h to 37FFFFh 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3F9FFFh 3FA000h to 3FBFFFh 3FC000h to 3FDFFFh 3FE000h to 3FFFFFh
15
MB84SD23280FA/MB84SD23280FE-70
* Sector Protection Verify Autoselect Codes Table Type Manufacture's Code Device Code Extended Device Code*1 Sector lock/ unlock A21 to A13 BA*2 BA* BA BA Sector Addresses
2
A7 L L L L L
A6 L L L L L
A5 L L L L L
A4 L L L L L
A3 L L H H L
A2 L L H H L
A1 L L H H H
A0 L H L H L
Code (HEX) 04h 227Eh 2224h 2201h 01h*2
Legend: L = VIL, H = VIH. See "sDC CHARACTERISTICS" for voltage levels. *1: A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh *2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
16
MB84SD23280FA/MB84SD23280FE-70
* Flash Memory Command Definitions
Command Sequence Read / Reset Read / Reset Autoselect Program Chip Erase Sector Erase Erase Suspend Erase Resume Fast Program Set to Fast Mode Reset from Fast Mode *1 Sector Lock/Unlock Query Bus Write Cycles Req'd 1 3 3 4 6 6 1 1 2 3 2 3 1 First Bus Write Cycle XXXh 555h 555h 555h 555h 555h BA BA XXXh 555h BA XXXh (BA) 55h F0h AAh AAh AAh AAh AAh B0h 30h A0 AAh 90h 60h 98h Second Write Cycle RA 2AAh 2AAh 2AAh 2AAh 2AAh -- -- PA 2AAh RD 55h 55h 55h 55h 55h -- -- PD 55h 555h -- SLA -- 20h -- 60h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Third Write Fourth Write Cycle Cycle -- 555h (BA) 555h 555h 555h 555h -- -- -- F0h 90h A0h 80h 80h -- -- -- RA -- PA 555h 555h -- -- -- RD -- PD AAh AAh -- -- Fifth Write Cycle -- -- -- -- 2AAh 2AAh -- -- -- -- -- -- 55h 55h -- -- Sixth Write Cycle -- -- -- -- 555h SA -- -- -- -- -- -- 10h 30h -- --
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
XXXh F0h*2 XXXh -- 60h --
Legend: RA = Address of the memory location to be read. PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, and A14 will uniquely select any sector. BA = Bank Address. Address setted by A22, A21 will select Bank A, Bank B, Bank C and Bank D. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of write pulse. CR = Configuration Register address bits A19 to A12. *1: This command is valid during Fast Mode. *2: The data "00h" is also acceptable. Notes: * Address bits A21 to A11 = X = "H" or "L" for all address commands except for PA, SA, BA. * Bus operations are defined in "s DEVICE BUS OPERATION". * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
17
MB84SD23280FA/MB84SD23280FE-70
2. AC Characteristics
* Read Operations Parameter Access Time from CEf Low Access Time *1 Output Enable to Output Valid Output Enable Hold Time Read Toggle and Data Polling -- -- tOEH tOEZ Symbol JEDEC -- -- -- Standard tCE tACC tOE Min 0 10 Value Max 70 70 20 10 Unit ns ns ns ns ns ns
Output Enable to High-Z *2
*1 : Access Time is from the last of either stable addresses. *2 : Not 100% tested. * Hardware Reset (RESET) Parameter RESET Pin Low (During Embedded Algorithms) to Read Mode* RESET Pin Low (NOT During Embedded Algorithms) to Read Mode* RESET Pulse Width Reset High Time Before Read* RESET Low to Standby Mode * : Not 100% tested. Symbol JEDEC -- -- -- -- -- Standard tREADY tREADY tRP tRH tRPD Min 500 200 20 Value Max 20 500 Unit s ns ns ns s
18
MB84SD23280FA/MB84SD23280FE-70
* Erase/Program Operations Symbol Parameter JEDEC Write Cycle Time*1 Address Setup Time*2 Address Hold Time*2 Data Setup Time Data Hold Time Read Recovery Time Before Write CE Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation*3 Sector Erase Operation*3, *4 tWHWH2 Chip Erase Operation*3, *4 VCC Setup Time CE Setup Time to WE *1 : Not 100% tested. *2 : Addresses are latched on the falling edge of WE. *3 : See the "Erase and Programming Performance" section in "BDS64xF" datasheet for more information. *4 : Does not include the preprogramming time. -- tELWL tVCS tCS tWHWH2 tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tWHEH tEHWH tWHWL -- tWHWH1 Standard tWC tAS tAH tDS tDH tGHWL tCH tWP tWPH tSR/W tWHWH1 Min 80 0 45 45 0 0 0 50 30 0 50 0 Typ 8 0.5 67.0 Max ns ns ns ns ns ns ns ns ns ns s s s ns Value Unit
19
MB84SD23280FA/MB84SD23280FE-70
3. Erase and Programming Performance
Value Parameter Min Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle -- -- -- 100,000 Typ 0.5 6 25.2 -- Max 2.0 100 95 -- s s s cycle Excludes programming prior to erasure Excludes system level overhead Excludes system level overhead -- Unit Comments
Note: Typical Erase Conditions: TA = + 25C, VCCf = 1.8 V Typical Program Conditions: TA = + 25C, VCCf = 1.8 V, Data = checker
20
MB84SD23280FA/MB84SD23280FE-70
* Read Mode
CEf
OE
tOEH
tOE
WE DQ15 to DQ0
tCE
tOEZ Valid RD
tACC
A21 to A0
tCAS
RA
Note: RA = Read Address, RD = Read Data.
* Reset Timings
CEf, OE
tRH
RESET
tRP tREADY Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
CEf, OE
tREADY
RESET
tRP
21
MB84SD23280FA/MB84SD23280FE-70
* Program Operation Timings
Program Command Sequence (last two cycles) Read Status Data
Address Data
555h
PA
VA In Progress
VA
A0h tDS tDH
PD
Complete
CEf
OE
tWP
tCH
WE
tWHWH1 tCS tWC tVCS tWPH
VCCf
Notes : * PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. * "In progress" and "complete" refer to status of program operation in "MBM29BS64LF" Data sheet. * A21 to A12 are don't care during command sequence unlock cycles.
22
MB84SD23280FA/MB84SD23280FE-70
* Chip/Sector Erase Command Sequence
Erase Command Sequence (last two cycles)
Read Status Data
Address Data
2AAh 555h for chip erase 555h/55h
SA 10h for chip erase 10h/30h tDS tDH
VA In Progress
VA
Complete
CEf
OE
tWP
tCH
WE
tWHWH2 tCS tWPH tWC tVCS
VCCf
Notes : * SA is the sector address for Sector Erase. * Address bits A21 to A12 are don't cares during unlock cycles in the command sequence.
23
MB84SD23280FA/MB84SD23280FE-70
* Data Polling Timings (During Embedded Algorithm)
tCE
tCEZ
CEf
tCH tOE tOEZ
OE
tOEH
WE
tACC
Address
VA
VA
Status Data
Status Data
Note : VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data Polling will output true data.
24
MB84SD23280FA/MB84SD23280FE-70
* Toggle Bit Timings (During Embedded Algorithm)
tCE
tCEZ
CEf
tCH tOE tOEZ
OE
tOEH
WE
tACC
Address
VA
VA
Status Data
Status Data
Note : VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling.
25
MB84SD23280FA/MB84SD23280FE-70
* Bank-to-Bank Read/Write Cycle Timings
Last Cycle in Program or Sector Erase Command Sequence tWC Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence
tRC
tRC
tWC
CEf
OE
tOE tOEH tGHWL
WE
tWPH tWP tDS tDH PD/30h tSR/W tACC tOEZ tOEH RD RD AAh
Data
Address
PA/SA
RA
RA
555h
Note: Break points in waveforms indicate that system may alternately read array data from the "non-busy bank" while checking the status of the program or erase operation in the "busy" bank. The system should read status twice to ensure valid information.
26
MB84SD23280FA/MB84SD23280FE-70
s 8M SRAM for MCP 1.8 V
1. AC Characteristics
* Read Cycle (SRAM) Parameter Read Cycle Time Address Access Time Chip Enable (CE1s) Access Time Chip Enable (CE2s) Access Time Output Enable Access Time LB, UB to Output Valid Chip Enable (CE1s Low and CE2s High) to Output Active Output Enable Low to Output Active LB, UB Enable Low to Output Active Chip Enable (CE1s High or CE2s Low) to Output High-Z Output Enable High to Output High-Z LB, UB Output Enable to Output High-Z Output Data Hold Time Note: Test Conditions-Output Load:1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 1.8 V Timing measurement reference level Input: 0.5 x VCCs Output: 0.5 x VCCs Symbol tRC tAA tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Value Min 70 -- -- -- -- -- 5 0 5 -- -- -- 5 Max -- 70 70 70 35 70 -- -- -- 25 25 25 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
27
MB84SD23280FA/MB84SD23280FE-70
* Read Cycle (SRAM)
tRC
Address
tAA tCO1 tOH
CE1s
tCOE tCO2 tOD
CE2s
tOD tOE
OE
tOEE tODO
LB, UB
tBA tBE tCOE tBD
DQ
Valid Data Output
Note: WE remains High for the read cycle.
28
MB84SD23280FA/MB84SD23280FE-70
* Write Cycle (SRAM) Parameter Write Cycle Time Write Pulse Width CE1s to End of Write CE2s to End of Write Address valid to End of Write LB, UB to End of Write Address Setup Time Write Recovery Time WE Low to Output High-Z WE High to Output Active Data Setup Time Data Hold Time Symbol tWC tWP tCW1 tCW2 tAW tBW tAS tWR tODW tOEW tDS tDH Value Min 70 55 55 55 55 55 0 0 -- 0 30 0 Max -- -- -- -- -- -- -- -- 25 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
29
MB84SD23280FA/MB84SD23280FE-70
* Write Cycle*1 (WE control) (SRAM)
tWC Address tAS tWP tWR
WE tAW tCW CE1s
CE2s
tCW
tBW LB, UB tODW tOEW
DOUT
*2 tDS tDH
*3
DIN
*4
Valid Data Input
*4
*1 : If OE is High during the write cycle, the outputs will remain at high impedance. *2 : If CE1s goes Low (or CE2s goes High) coincident with or after WE goes Low, the output will remain at high impedance. *3 : If CE1s goes High (or CE2s goes Low) coincident with or before WE goes High, the output will remain at high impedance. *4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
30
MB84SD23280FA/MB84SD23280FE-70
* Write Cycle*1 (CE1s control) (SRAM)
tWC Address tAS tWP tWR
WE tAW tCW CE1s
CE2s
tCW
tBW LB, UB tBE tCOE DOUT tDS tDH tODW
DIN
*2
Valid Data Input
*2
*1: If OE is High during the write cycle, the outputs will remain at high impedance. *2: Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
31
MB84SD23280FA/MB84SD23280FE-70
* Write Cycle*1 (CE2s Control) (SRAM)
tWC Address tAS tWP tWR
WE
tCW CE1s
tAW CE2s tCW
tBW LB, UB tBE tCOE DOUT tDS DIN *2 tDH tODW
Valid Data Input
*2
*1 : If OE is High during the write cycle, the outputs will remain at high impedance. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
32
MB84SD23280FA/MB84SD23280FE-70
* Write Cycle*1 (LB, UB Control) (SRAM)
tWC Address tWP WE tWR
tCW CE1s
tCW CE2s tAW tAS tBW
LB, UB
tBE tCOE DOUT tDS *2 tDH *2 tODW
DIN
Valid Data Input
*1 : If OE is High during the write cycle, the outputs will remain at high impedance. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
33
MB84SD23280FA/MB84SD23280FE-70
2. Data Retention Characteristics (SRAM)
Parameter Data Retention Supply Voltage Standby Current Chip Deselect to Data Retention Mode Time Recovery Time Note : tRC: Read cycle time * CE1s Controlled Data Retention Mode *1 VDH = 1.8 V Symbol VDH IDDS2 tCDR tR Value Min 1.0 -- 0 tRC Typ -- 0.3 -- -- Max 1.95 14 -- -- Unit V A ns ns
VCCs 1.65 V
DATA RETENTION MODE
VIH VDH CE1s
*2
*2
VCCS - 0.2 V tCDR tR
VSS
*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to VCCs-0.2 V or VSS to 0.2 V during data retention mode. Other input and input/output pins can be used between -0.3 V to VCCs+0.3 V. *2 : When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition of VCCs from Vccs Max to VIH Min level.
34
MB84SD23280FA/MB84SD23280FE-70
* CE2s Controlled Data Retention Mode*
VCCs
DATA RETENTION MODE 1.65 V
VDH VIH CE2s VIL
tCDR
tR
0.2 V
VSS
* : In CE2s controlled data retention mode, input and input/output pins can be used between -0.3 V to Vccs+0.3 V.
35
MB84SD23280FA/MB84SD23280FE-70
s PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Setup VIN = 0 VOUT = 0 VIN = 0 Value Min -- -- -- Typ -- -- -- Max 16.0 22.0 18.0 Unit pF pF pF
Note : Test conditions TA = + 25 C, f = 1.0 MHz
s HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
s CAUTION
* The high voltage (VID) cannot apply to address pins and control pins.
36
MB84SD23280FA/MB84SD23280FE-70
s ORDERING INFORMATION
MB84SD23280 FA/E -70 PBS
PACKAGE TYPE PBS = 73-ball FBGA SPEED OPTION
Device Revision
DEVICE NUMBER/DESCRIPTION 64 Mega-bit (4 M x 16-bit) Dual Operation Flash Memory 1.8 V-only Read, Program, and Erase 8 Mega-bit (512K x 16-bit) SRAM
37
MB84SD23280FA/MB84SD23280FE-70
s PACKAGE DIMENSION
73-ball plastic FBGA (BGA-73P-M03)
11.600.10(.457.004) 0.20(.008) S B B 1.19 .047 (Seated height)
+0.15 -0.10 +.006 -.004
0.40(.016) REF
0.80(.031) REF 10
0.80(.031) REF A 8.000.10 (.315.004)
9 8 7 6
0.40(.016) REF 0.10(.004) S
5 4 3 2 1
INDEX-MARK AREA
0.390.10 (Stand off) (.015.004) S 0.20(.008) S A
M
L
K
J
H
G
F
E
D
C
B
A
INDEX BALL 73-o0.45 -.005 73-o0.18 -.002
+0.10 +.004
o0.08(.003)
M
S AB
0.10(.004) S
C
2003 FUJITSU LIMITED B73003S-c-1-1
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
38
MB84SD23280FA/MB84SD23280FE-70
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0311 (c) FUJITSU LIMITED Printed in Japan

▲Up To Search▲

Price & Availability of MB84SD23280FE-70

	To Download MB84SD23280FE-70 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .